The present invention relates to a programming method of a flash memory device and, more particularly, to a programming method of a flash memory device, in which 2-bits or more of data are stored in one memory cell.
A flash memory device may be a NOR and a NAND type device. The NAND flash memory device is advantageous because it supports a higher level of integration than that of the NOR flash memory device. A memory cell array of a NAND flash memory device includes a plurality of memory cell blocks. This is described in more detail below.
FIG. 1 is a circuit diagram illustrating a memory cell block of a NAND flash memory device.
Referring to FIG. 1, a memory cell block includes a plurality of cell strings ST. The cell strings are connected to bit lines BL1 to BL3 (only three bit lines are illustrated to simplify description).
Each cell string has a structure in which a drain select transistor DST, a plurality of memory cells C0-1 to Cn and a source select transistor SST are connected in series. A drain of the drain select transistor DST included in each cell string is connected to a corresponding bit line and a source of the source select transistor SST is connected to a common source line CSL. Gates of the drain select transistors DST included in the respective cell strings are interconnected to form a drain select line DSL, and gates of the source select transistors SST are interconnected to form a source select line SSL. Gates of memory cells are interconnected to form word lines WL0 to WLn.
To store data in the flash memory cell described above, a programming operation is performed. During the programming operation, a high program voltage of 15V or higher is applied to a selected word line (for example, WL0), and a pass voltage is applied to the unselected word lines irrespective of an erase state or a program state so that the memory cell is activated. Bit lines are applied with a ground voltage 0V.
During the programming operation, a memory cell of a plurality of memory cells C0-1 to C0-3 that share the word line WL0 is in an erase state (hereinafter, referred to as a “program-inhibited cell”). A program-inhibited voltage (for example, Vcc) is applied to a bit line BL2 connected to a string ST including a program-inhibited cell (for example, C0-2) that is in the erase state as described above. A channel region of the program-inhibited cell C0-2 is precharged to the program-inhibited voltage. If a program voltage is applied to a word line, the voltage of a channel region is raised by channel boosting, such that a programming operation is not performed.
A programming method of storing 2-bit data in one memory cell has recently been developed. Before a programming operation is performed, an erase operation of a memory cell block is performed, so that the memory cells are in an erase state. In general, all of the memory cells store 11 data in the erase state. The programming method of storing 2-bit data is performed through several programming operations, and includes a LSB programming operation of changing the 2-bit data from 11 to 10, and a MSB programming operation of changing the 2-bit data from 11 to 01 or from 10 to 00.
Generally, after the LSB programming operation and the MSB programming operation are sequentially performed on a selected word line, they are performed on a next word line. However, during the programming operation, the threshold voltage of a memory cell connected to a word line adjacent to the selected word line can be changed due to an interference phenomenon between memory cells. To minimize the change of the threshold voltage, the sequence of the LSB programming operation and the MSB programming operation and the sequence of word lines may be changed.
If the sequence is changed as described above, a memory cell C2-2 located between the drain select transistor DST and a memory cell (for example, C1-2) connected to a selected word line, can be first programmed during a programming operation. In this case, the channel region of the memory cell C0-2 located between the source select transistor SST and the memory cell C1-2 connected to a selected word line is precharged to a low level, such that a channel voltage does not rise to a target voltage. Thus, a voltage difference between the word line WL0 and the channel region of the memory cell C0-2 is lowered, so that a programming operation of the memory cell C0-2 is performed even though the programming operation should not be performed. Consequently, the threshold voltage may rise.